A) Field of the Invention
The present invention relates to a semiconductor wafer device and its manufacture method, and more particularly to a semiconductor wafer device having a damascene wiring structure and its manufacture method.
In this specification, an etching stopper layer is intended to mean a layer having an etch rate of one fifth or smaller than an etch rate of another layer under etching, in order that even if the etching stopper layer is exposed during etching, this etching stopper layer is prevented from being etched excessively.
B) Description of the Related Art
A higher integration density of semiconductor devices is desired increasingly. Conventionally, a wiring pattern is formed by forming an A1 wiring layer or a W wiring layer on an insulating layer, thereafter forming an etching mask made of a resist pattern or the like on the wiring layer, patterning the wiring layer and embedding it with another the insulating layer.
As the integration density becomes high, there is an increasing need to narrow a width of a wiring pattern and a pitch between wiring patterns. Such fine patterning is now confronted in some cases to a limit in the techniques of forming a wiring pattern by directly pattering a wiring layer. This process is gradually replaced by a damascene wiring process by which a wiring groove and a via hole are formed in an insulating layer, a wiring layer is deposited on the insulation film, being filled in these wiring groove and via hole, and an unnecessary wiring layer on the top surface of the insulating layer is removed by chemical mechanical polishing (CMP).
As the wiring material, Cu is used recently which has a lower resistivity and a higher electro migration resistance than A1, A1 alloy, W and the like. Although Cu provides excellent performances as the wiring material, it is likely to be oxidized forming an oxide film thereon, the oxide being not as chemically stable as the oxide of A1. It is necessary therefore to pay attention to a wiring structure and a wiring forming process.
As a damascene process of connecting upper and lower wiring patterns by a via conductor, a single damascene process and a dual damascene process are known. In the single damascene process, a via hole is formed through a lower interlevel insulating film a via conductor is filled in the via hole, thereafter an upper interlevel insulating film is formed, a wiring groove is formed, and then a wiring pattern is filled in the wiring groove. In the dual damascene process, after a via hole and a wiring groove are formed in an interlevel insulating film, wiring material is filled in the via hole and wiring groove at the same time.
As the dual damascene process, there are a first-via type that a via hole is first formed and then a wiring groove is formed and a last-via type that a via hole is formed after a wiring groove is formed.
As the wiring density becomes high, a capacitance between wiring patterns is likely to become high. As the capacitance of a wiring pattern becomes high, a signal transmission speed lowers. In order to reduce the capacitance of a wiring pattern, it is effective to lower the dielectric constant of an insulating layer. In addition to a conventional silicon oxide insulating layer, other insulating layers have been used recently, such as: an insulating layer made of silicon oxide doped with fluorine or carbon; an insulating layer made of coating type hydrocarbon-containing organic insulating material; an insulating layer made of coating type inorganic insulating material; and a porous insulating layer containing voids.
These wiring techniques have not been developed sufficiently. It may occur that if techniques are improved in one aspect, a problem at another point occurs and a percentage of defective devices increases.